Optimal Clocking of Synchronous Digital Circuits
نویسنده
چکیده
We introduce two CAD tools, checkT, and minT, , for timing verification and optimal clocking. Both tools are based on a new timing model of synchronous digital circuits which is: 1) general enough to handle arbitrary multiphase clocking; 2) complete, in the sense that it captures signal propagation along short as well as long paths in the logic; 3) extensible to make it relatively easy to incorporate “complex” latching structures; and 4) notationally simple to make it amenable to analytic treatment in some important special cases. We are currently using these tools to help in the design of a 4ns gallium arsenide micro-supercomputer.
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تاریخ انتشار 2004